Almandine OS v0.1
Single Static Binary • Zero Runtime Dependencies

Layered Software Architecture & Zero Copy 2 MiB WB Arena

From pure x86_64 assembly control register bootstrap to the quantized Unnamed model forward pass, the entire Almandine OS stack links into a single freestanding PE32+ image with zero dynamic heap fragmentation or page table churn.

LAYER 4 • APPLICATION & UNNAMED MODEL ENGINE src/app/model_repl.cpp

Unnamed model Transformer Forward Pass & Interactive REPL

Streams GGUF v3 payloads from NVMe or GPT Partition 2 in 16 MiB chunks, binds tensors zero copy in RAM, runs SentencePiece longest match BPE tokenization, and executes RMSNorm, per head Q/K/V Norm, RoPE, Grouped Query Attention (GQA), GeGLU FFN, and logit softcapping (softcap · tanh(logit / softcap)).

model_try_autoload() model_tokenize() model_forward_token() model_chat_turn()
LAYER 3 • QUANTIZED COMPUTE BRIDGE src/uefi_shim/ggml_baremetal.c + third_party/llama.cpp/

8 P Core Q4_K_M × Q8_K Matrix Vector Dispatcher

Links upstream ggml-cpu (arch/x86/quants.c) directly into BOOTX64.EFI. Initializes hardware F16C lookup tables, quantizes FP32 activations into block_q8_K once on the BSP, and partitions Q4_K_M weight rows across 8 physical P cores on 16 row (64 byte cache line) boundaries.

ggml_baremetal_init() ggml_baremetal_mul_mat_q4_K_f32() ggml_vec_dot_q4_K_q8_K() quantize_row_q8_K()
LAYER 2 • BARE METAL OS SHIM & RUNTIME efi_main.c • ansi_console.c • mp_dispatch.c • libc_freestanding.c

UEFI Orchestrator, Lock Free MP Spin Pool & Freestanding Libc/Libm

Disables the 5 minute UEFI watchdog, calibrates the CPU TSC, binds USB/PS2 keyboards recursively via ConnectController, wakes APs via EFI_MP_SERVICES_PROTOCOL, parks E cores, and manages the 2 MiB aligned Write Back page arena and hardware SIMD math primitives (expf, sqrtf, tanhf).

efi_main() mp_init_pool() mp_parallel_for() arena_alloc_aligned() kprintf()
LAYER 1 • x86_64 ASSEMBLY BOOTSTRAP src/uefi_shim/cpu_init.S

Pre C Control Register Unlock & KVM Guarded Intel HWP MSRs

Executes at /entry:efi_start and ap_asm_trampoline before any C function prologue can emit VEX encoded instructions. Unlocks CR0.MP, CR4.OSFXSR, CR4.OSXSAVE, and XCR0 = 0x07 (256 bit YMM0 to YMM15), inspects CPUID.1AH hybrid core types, and programs High Performance hardware P-States via Intel HWP Speed Shift MSRs.

efi_start ap_asm_trampoline cpu_init_core ___chkstk_ms cpu_cli / cpu_sti

Physical RAM: 2 MiB Aligned Write Back Arena (g_arena_base)

Allocated via BS->AllocatePages(EfiLoaderData) • 64 Byte & 4 KiB Aligned
1. Boot Self Test & Block IO Probe Buffers 4 KiB DMA Aligned
  • 64 MiB (4 × 16 MiB) AVX2 streaming pipeline verification buffers
  • UEFI EFI_BLOCK_IO_PROTOCOL sector probe buffer (0x46554747 "GGUF" magic scan)
2. Raw GGUF v3 Model Payload (Zero Copy Bound) 16 MiB Chunked Stream
  • GGUF Header + KV Metadata + Vocabulary Strings (zero copy string refs)
  • token_embd.weight (GGML_TYPE_Q4_K): direct pointer in g_model
  • blk.0..N.attn_* & blk.0..N.ffn_* (Q4_K / F32): 32 byte aligned tensor data
  • output_norm.weight (F32) + output.weight (Q4_K)
3. Grouped Query Attention (GQA) KV Cache Arena 64 Byte Cache Line Aligned
  • k_cache: [n_layer][MAX_SEQ_LEN][n_head_kv * head_dim] (FP32 contiguous)
  • v_cache: [n_layer][MAX_SEQ_LEN][n_head_kv * head_dim] (FP32 contiguous)
4. Transformer Activation Scratchpad 64 Byte Cache Line Aligned
  • x_cur, x_norm, attn_out [n_embd] & q_buf, k_buf, v_buf
  • ffn_gate_buf, ffn_up_buf [n_ff] (GeGLU intermediate states)
  • work_q8 [max_dim / 256] (block_q8_K quantized activation vector)
  • logits [n_vocab] (FP32 softcapped output distribution)
/* Lock-Free 8-P-Core Dispatch (mp_dispatch.c) */ quantize_row_q8_K(x_f32, work_q8_k, K); cpu_cli(); // Mask UEFI timer IRQ jitter on BSP during matmul g_ctrl.fn = q4_k_matvec_worker; g_ctrl.workers_done = 0; atomic_inc(&g_ctrl.epoch); // Wake 7 spinning P-core APs immediately q4_k_matvec_worker(0); // BSP computes slice 0 via ggml_vec_dot_q4_K_q8_K while (g_ctrl.workers_done < 7) cpu_pause(); cpu_sti();
Validated on Intel Core i9 & Xeon Scalable

Intel Core i9 & Xeon Bare Metal Silicon Engineering

Without a Linux kernel, UEFI leaves CR4.OSXSAVE = 0, clocks pinned to base BIOS ratios, and hybrid E cores competing for package TDP. Almandine OS configures the processor's SIMD vector registers, hybrid topology, and autonomous Power Control Unit directly in Ring 0.

1. Pre C Assembly AVX2 Bootstrap

CR4.OSXSAVE • XCR0=0x07

When compiled with -march=x86-64-v3 -mavx2, Clang emits VEX encoded vmovups/vxorps instructions inside C function prologues. Because UEFI boots with CR4.OSXSAVE = 0 (0x00000668), calling any C function immediately triggers an Invalid Opcode (#UD, Exception 6) crash. Almandine OS solves this in pure assembly (efi_start and ap_asm_trampoline) before jumping to C.

# src/uefi_shim/cpu_init.S: Unlock YMM0..YMM15 pre-C movq %cr4, %rax orq $0x40600, %rax # Set OSFXSR (Bit 9) | OSXMMEXCPT | OSXSAVE (Bit 18) movq %rax, %cr4 xorl %ecx, %ecx xgetbv orl $0x07, %eax # Enable x87 (Bit 0) + SSE XMM (Bit 1) + AVX YMM (Bit 2) xsetbv

2. AVX VNNI & Dual Port FMA3 Compute

VPDPBUSD • VFMADD231PS

Each Raptor Cove P core features two 256 bit FMA execution units on Ports 0 & 1 (32 FP32 FLOPs/cycle/core, >1.3 TFLOPS theoretical across 8 P cores). For quantized Q4_K_M × Q8_K dot products, AVX VNNI fuses 32 lane unsigned 8 × signed 8 multiply accumulate into a single vpdpbusd instruction, replacing the 3 instruction AVX2 sequence and avoiding 16 bit saturation.

/* Standard AVX2 (3 instructions) vs AVX-VNNI (1 fused instruction) */ // AVX2: vpmaddubsw + vpmaddwd + vpaddd // VNNI: vpdpbusd ymm_acc, ymm_u8, ymm_i8 acc = _mm256_dpbusd_epi32(acc, u8_q4_weights, i8_q8_activations); sum = _mm256_fmadd_ps(v_scale_d, _mm256_cvtepi32_ps(acc), sum);

3. KVM Guarded Intel HWP Speed Shift

MSR 0x1A0 → 0x770 → 0x774

Without an OS scheduler timer, legacy ACPI P states leave the CPU stuck at base clock. cpu_init.S checks CPUID.01H:ECX[31] (skipping MSR writes inside QEMU/KVM to prevent #GP(0) faults) and programs High Performance hardware P-States with EPP = 0x00 and Max = 0xFF so the on die PCU microcontroller scales P cores to full turbo boost in <1 ms.

/* IA32_HWP_REQUEST (MSR 0x774) Bare-Metal Configuration */ Bits [7:0] Minimum_Perf = Guaranteed_Perf (from MSR 0x771[15:8]) Bits [15:8] Maximum_Perf = 0xFF (Unlocks High-Performance Turbo Ceiling) Bits [23:16] Desired_Perf = 0x00 (Hardware Autonomous PCU Scaling) Bits [31:24] EPP = 0x00 (Maximum Performance / Fastest Ramp)

4. Hybrid P Core Pinning & E Core Parking

CPUID.1AH • 0x40 vs 0x20

On the 24 core (32 thread) Core i9 13980HX, 8 Raptor Cove P cores and 16 Gracemont E cores share a single package power budget (PL1/PL2). mp_dispatch.c inspects CPUID.1AH:EAX[31:24], enrolls only the 8 physical P cores (0x40), and parks all 16 E cores (0x20) and SMT siblings in hardware HLT sleep so 100% of TDP feeds AVX2 compute.

/* Hybrid Core Filter (src/uefi_shim/mp_dispatch.c) */ uint8_t core_type = (cpuid_1a_eax >> 24) & 0xFF; if (core_type == 0x40 && smt_thread_id == 0) { enroll_pcore_worker(apic_id); // Active 64B cache-line spin-pool } else { return_to_uefi_hlt_sleep(); // 0W dynamic draw on 16 E-cores }

Bare Metal Hardware Bottlenecks & Ring 0 Mitigations

Source: docs/performance_issues.md
Subsystem Firmware / Hardware Pitfall Untuned Penalty Almandine OS Ring 0 Resolution
1. MTRR / PAT Caching Buggy laptop BIOSes leave upper physical RAM (>4 GiB) Uncached (UC, 0x00) in Variable MTRRs 10× to 80× slower Audit MSR 0x2FF (IA32_MTRR_DEF_TYPE) & MSR 0x277 (IA32_PAT); enforce Write Back (WB, 0x06) on all RAM across BSP & 7 APs
2. Package Power (PL1/PL2) Pre OS Embedded Controller clamps MSR_PKG_POWER_LIMIT (0x610) to 35W to 45W 25% to 45% slower Read MSR 0x606 units; if PKG_LOCK (bit 63) is clear, program MSR 0x610 to PL1 = 115W / PL2 = 157W
3. L2 / DCU Prefetchers BIOS leaves hardware stream prefetchers disabled in MSR 0x1A4 15% to 30% slower Clear bits 0..3 of MSR_MISC_FEATURE_CONTROL (0x1A4) on all 8 P cores to prefetch 256 weight Q4_K_M super blocks
4. DTLB Thrashing 4 KiB pages across a ~16 GB model overflow the 2048 entry L2 STLB (covers only 8 MiB) 8% to 15% slower Coalesce CR3 page tables covering g_arena_base into 2 MiB (PS=1) or 1 GiB hugepages
5. Cache Line False Sharing Adjacent P cores writing to the same 64 byte output line during mul_mat 5% to 12% slower Partition per core output row ranges (ir0..ir1) on 16 float (64 byte) cache line boundaries
6. UEFI DXE Timer Jitter UEFI background timer interrupts stalling the 8 core barrier mid token 2% to 5% jitter Mask interrupts (cli/sti) on BSP during mp_parallel_for and transition to ExitBootServices()